FIG. 1 illustrates a conventional memory device 100 in which column redundancy is used to bypass defects in a memory array. In a typical implementation, the device 100 includes a quarter memory array 110, and one or more adjacent column redundancy (“CR”) structures 120. The memory array 110 includes numerous column arrays, each of which are coupled to a further number of memory cells (not shown). In memory devices which use matched loading of sense- and reference-side signals, the CR structure 120 will include two addressable columns or “slices” (conventionally referred to as an “even” and “odd slices”), which are designed to replace sense and load side columns that correspond to a defective array column.
Once a defective array column 112 is identified, it is bypassed by mapping the address of the defective column to the address of one of the slices within the CR structure 120. The address of the defective array column 112 may be routed to either of the even or odd CR slices, and the reference or load signal is address mapped to the remaining CR slice in the CR structure 120. An array controller (not shown) typically performs the address mapping functions. The CR structure 120 then serves as a replacement for the defective array column 112 during operation of the memory device 100, whereby one of the CR slices serves as the storage or sense side of the defective array column 112, and the other CR slice serving as the reference or load side associated with the defective array column 112.
While effective in replacing defective column arrays, the conventional approach suffers from disadvantages resulting from the single and dedicated use of a CR structure to replace one column defect. In particular, while the CR structure 120 includes two columns capable of storage, only one slice is used for memory storage; the second slice being used only as a reference or load for the first slice. Accordingly, fifty percent of the CR structure 120 goes unused.
What is therefore needed is an improved memory device architecture and corresponding method for re-using CR structures to replace column defects in a memory device.